diff --git a/arch/arm/mach-msm/acpuclock.c b/arch/arm/mach-msm/acpuclock.c index 0eda940..29a669f 100644 --- a/arch/arm/mach-msm/acpuclock.c +++ b/arch/arm/mach-msm/acpuclock.c @@ -248,10 +248,18 @@ static int acpuclk_set_vdd_level(int vdd) /* Set proper dividers for the given clock speed. */ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { - uint32_t reg_clkctl, reg_clksel, clk_div; + uint32_t reg_clkctl, reg_clksel, clk_div, a11_div; /* AHB_CLK_DIV */ clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; + + a11_div=hunt_s->a11clk_src_div; + + if(hunt_s->a11clk_khz>=528000) { + a11_div=0; + writel(0x25, MSM_CLK_CTL_BASE+0x33C); + udelay(50); + } /* * If the new clock divider is higher than the previous, then * program the divider before switching the clock @@ -274,7 +282,7 @@ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { /* Program clock divider */ reg_clkctl = readl(A11S_CLK_CNTL_ADDR); reg_clkctl &= ~0xf; - reg_clkctl |= hunt_s->a11clk_src_div; + reg_clkctl |= a11_div; writel(reg_clkctl, A11S_CLK_CNTL_ADDR); /* Program clock source selection */ @@ -293,7 +301,7 @@ static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { /* Program clock divider */ reg_clkctl = readl(A11S_CLK_CNTL_ADDR); reg_clkctl &= ~(0xf << 8); - reg_clkctl |= (hunt_s->a11clk_src_div << 8); + reg_clkctl |= (a11_div << 8); writel(reg_clkctl, A11S_CLK_CNTL_ADDR); /* Program clock source selection */